1. Field of the Invention
The present invention relates to electronics, and, in particular, to charge-pump phase-locked loops and other signal synthesizers having loop filters with capacitors.
2. Description of the Related Art
A phase-locked loop (PLL) is a circuit that generates a periodic output signal that has a constant phase relationship with respect to a periodic input signal. PLLs are widely used in many types of measurement, microprocessor, and communication applications. One type of phase-locked loop is the charge-pump PLL, which is described in Floyd M. Gardner, “Charge-Pump Phase-Lock Loops,” IEEE Trans. Commun., vol. COM-28, pp. 1849–1858, November 1980, the teachings of which are incorporated herein by reference.
FIG. 1 shows a block diagram of a conventional charge-pump phase-locked loop 100. Phase detector (PD) 102 compares the phase θIN of an input signal to the phase θFB of a feedback signal and generates an error signal: either an UP signal U (when θIN leads θFB) or a DOWN signal D (when θFB leads θIN), where the width of the error signal pulse indicates the magnitude of the difference between θIN and θFB.
Charge pump 104 generates an amount of charge q equivalent to the error signal (either U or D) from PD 102. Depending on whether the error signal was an UP signal or a DOWN signal, the charge q is either added to or subtracted from one or more capacitors in loop filter 106. In a typical implementation, loop filter 106 operates as an integrator that accumulates the net charge from charge pump 104. As shown in FIG. 1, loop filter 106 generates two inputs for voltage-controlled oscillator (VCO) 108: a low-gain input VCTRL and a high-gain input VBG. A voltage-controlled oscillator is a device that generates a periodic output signal (FOUT in FIG. 1), whose frequency is a function of the VCO input voltages VCTRL and VBG, where the high-gain input voltage VBG is used to set the center frequency during calibration and the low-gain input voltage VCTRL serves as the steady-state signal path. In addition to being the output signal from PLL 100, the VCO output signal FOUT is used to generate the feedback signal for PD 102.
Optional input and feedback dividers 110 and 112 may be are placed in the input and feedback paths, respectively, if the frequency of the output signal FOUT is to be either a fraction or a multiple of the frequency of the input signal FIN.
More information about PLLs like PLL 100 can be found in U.S. Pat. No. 5,942,949, the teachings of which are incorporated herein by reference.
As described previously, although not shown in FIG. 1, the loop filters of conventional charge-pump PLLs, such as PLL 100, are implemented using capacitors. In order for such PLLs to operate properly it is important to avoid the adverse affects of gate oxide leakage currents in those loop-filter capacitors. The conventional approach to avoid the adverse affects of such leakage currents is to use capacitors in the loop filter that have relative large oxide thicknesses (e.g., 50–70 Angstroms). Unfortunately, such capacitors require relatively large areas to implement. It would be desirable to implement loop filters in charge-pump PLLs using capacitors having relatively small oxide thicknesses (e.g., 17 Angstroms) and correspondingly relatively small implementation areas.